Active pixel sensors (APS) are used in many approaches to produce images for viewers in many different circumstances. Some particular examples include mobile phone cameras and digital cameras. Active pixel sensors or image sensors are generally found in arrays of rows and columns, each sensor having a photo detector that outputs a light signal indicative of the light illuminating that pixel. The output is then converted into an electrical signal to be stored or used in other ways.
The image sensors may encounter a wide range of illumination intensities. In certain high illumination levels, the pixel may become saturated. One would thus expect the output of that sensor to represent a white level for that part of the scene. However this is not always the case and conventional CMOS APS image can sometimes show the brightest part of the scene as black or grey.
The effect comes from the double sampling nature of such images. Referring to FIG. 1, this effect will be described in more detail. A four transistor pixel 100 is shown connected to a column current source 110 and sampling capacitors 120. A typical operation of the process of a pixel including a reset, integration and a read step is as follows:                1. The photodiode 102 is reset by pulsing device 104;        2. As the voltage on device 104 falls the integration period begins;        3. At the end of the integration period of the pixel photo device 106 goes high and device 108 is pulsed such that the floating diffusion (FD node) 109 is reset;        4. The reset voltage of the FD node 109 is sampled via the source follower onto the Cblk capacitor of the sampling capacitors 120;        5. Device 104 is pulsed again and the charge from the photodiode is transferred to the FD node (and the FD voltage will reduce);        6. The signal value is sampled onto capacitor Csig of the sampling capacitors 120;        
During the sampling period the negative terminal of both Csig and Cblk are connected to ground. The brightness of any pixel in the array is proportional to the difference between Vblk and Vsig. However, if the illumination is sufficiently high the double sampling scheme can break down. The problem occurs with the blk value sampled in step 4 above and occurs because the FD node voltage can discharge due to light induced current. There will be a finite time between the reset pulse falling and the blk level being sampled in the column. If the illumination is sufficiently high, the FD node 109 can be partially or fully discharged by the time the level is sampled onto Cblk 120 in the column. This causes the difference between Vblk and Vsig to reduce for increasing illumination levels.
Once the blk and signal voltage levels have been sampled it is common for the difference to be converted to a digital word on-chip. This could be done by multiplexing Vblk and Vsig in the FIG. 1 example for each column to a single on-chip ADC or by using a single analog to digital converter (ADC) per column.
A single slope ADC 200 implementation shown in FIG. 2 will now be described in more detail. Assuming the reset level (blk) is greater that the signal level (Vblk>Vsig) the output of comparator 130 will initially be low.                1. The negative terminal of Csig is connected to a ramp generator (not shown) and begins to ramp up from OV.        2. Currently a counter begins to count up from zero.        3. As the ramp increases, the top plate of capacitor Csig also increases to maintain the same voltage across Csig.        4. When the non-inverting input of the comparator reaches the level of the inverting input the comparator will flip state and output a high state.        5. This will cause the current value of the counter 210 to be latched 220 into a bank of SRAM 230.The counter, latch, SRAM and comparator 130 form the basic elements of the ADC in this example.        
There have been a number of methods proposed for overcoming this artifacts problem. U.S. patent publication Ser. No. 2003/0133627 discloses a way of preventing the sampled voltages from the pixel falling below a predetermined level. If the column voltage falls below a certain level it will be clamped. However the clamp circuit that would allow it to operate is not provided. There is a suggestion that a revised clamp circuit would be relatively simple but maintaining the output after the sampling period would most certainly not.
U.S. Pat. No. 6,803,958 discloses an apparatus and method for eliminating artifacts in active pixel sensor (APS) imagers. The detection method is achieved by placing an additional comparator in the column and uses the output of the comparator to switch in an analog voltage which is known to be equal to a white level. A capacitor is used to hold the signal voltage prior to input to the additional comparator. The comparison element then adjusts the output voltage to a level which is equivalent to a saturated pixel.
This approach has a number of intrinsic problems associated therewith, and these are detailed below. An extra sample and hold capacitor is required in the column to hold the input to the comparator. This will require extra silicon area and will reduce the setting time of the column for a given column current due to the existence of an extra capacitor. An extra analog voltage is required that equates to a saturated level (Vaa). The comparator needs to be on for as long as the output signal is valid (the full ADC cycle id on-chip ADC used). This will increase the power consumption of the system
In addition, if this approach were to be used in a situation where pixels binning for column/row averaging were carried out there would need to be multiple elements which would greatly increase the system overheads. There would need to be additional capacitors voltage supply means and comparators. The resultant circuitry would become quite large and because there are many capacitors still further problems associated with settling time will be encountered.